(PLL) Phase Locked Loop is control system which generates output signals. Its phases have been related to phases of input signals. Whilst there are lots of various types, there is easy visualization initially as electronic circuit. It consists of phase detector and variable frequency oscillator. The oscillators do generate periodic signals. Phase detector in turn compares phases of those signals with phases of input periodic signals. This adjusts oscillators for keeping phases matched. For bringing output signals back towards input signals for comparing purposes is known as feedback loop. In this output is fed back towards input thereby forming loops. For keeping output and input phases in lock step implies also that it is keeping output and input frequencies same. Additional factors consequently to synchronized signals, Phase Locked Loop (PLL) could track input frequencies or it generates frequencies which is multiple of input frequencies. Such properties have been used for the computer clock’s frequency synthesis, synchronization and demodulation. Phase Locked Loop is employed widely in computers, radio, telecommunications and different electronic applications. It is used for demodulating signal, recovering signal from noisy channel of communication, generating stable frequencies at multiple of input frequency or distributing precise timed clock pulses in logic digital circuits like microprocessors. Single (IC) integrated circuit provides complete PLL’s building blocks. This technique is used widely in today’s electronic devices. This is with frequency of output from fractions of hertz to many gigahertzes.
Description: Phase detectors compare 2 input signals. It produces error signals that are proportional to its phase differences. Error signals are then filtered low-pass. Then used for driving VCO that create output phases. Outputs are fed by means of optional dividers back to inputs of systems. This produces negative feedback loop. In case output phase has been drifted, error signals shall increase. This drives VCO phases in opposite directions such that there is reduction of error. So output phases are locked to phases at different inputs. These inputs are called references. Analog Phase Locked Loop are built generally with low pass filter, VCO and analog phase detectors in turn placed in configuration of negative feedback. Digital PLL uses digital phase detectors. It has also dividers in feedback paths or in reference paths or both. This is for making output PLL signal frequency rational multiples of reference frequencies. Non-integer multiples of reference frequencies are created by replacement of simple divide-by-N counters in feedback paths with pulse programmable counters swallowing. This method is referred usually to as fractional-N PLL or fractional- N synthesizer.
Oscillator generates output periodic signals. You could make assumption that oscillator initially is nearly at same frequencies as reference signals. If phases from oscillators fall behind references, then phase detectors change oscillators control voltage such that it speeds up. Alike, if phase creeps ahead references, phase detectors change oscillators control voltage such that it slows down. Oscillator initially could be far from reference frequencies. Phase detectors practically respond to frequency difference such that there is increasing of lock in ranges of inputs allowable. Depending on applications, either controlled oscillator’s output or control signals to oscillators in turn provides output useful of PLL systems. Applications are clock recovery, deskewing, and clock generation. Parameters of performance are as follows: There should be order and type, holding in ranges, pulling in ranges (acquisition ranges and capture ranges) and locking in ranges. There has to be bandwidths of loop (defining of control loop speeds), transient responses (like settling time and overshoot for some accuracy) and steady state errors (like timing and remaining phase errors).
There has to be phase noises and output spectrum purity (like generation of sidebands from VCO tuning voltage tuning ripples.